This application is based on Japanese Patent Application 2001-031320, filed on Feb. 7, 2001, the entire contents of which are incorporated herein by reference.
1) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device for storing data by trapping carriers in the middle layer of a three-layer structure disposed above the channel region of an FET.
2) Description of the Related Art
FIG. 11A is a cross sectional view showing one example of a conventional flash memory cell. In a surface layer of a p-type silicon substrate 700, an n-type source region 701 and an n-type drain region 702 are formed. Between the source and drain regions, a channel region 703 is defined. The surfaces of the source and drain regions 701 and 702 are covered with a local oxide film 705.
On the surface of the channel region 703, a lamination film (hereinafter called an ONO film) 706 is formed which is made of a lower silicon oxide film 706A, a silicon nitride film 706B and an upper silicon oxide film 706C stacked in this order. A gate electrode 707 is formed on the local oxide film 705 and ONO film 706.
Next, the operation principle of the flash memory shown in FIG. 11A will be described.
In writing data, a source voltage Vs to be applied to the source region 701 and a substrate voltage Vsub are set to 0 V, a drain voltage Vd to be applied to the drain region 702 is set to 5 V, and a gate voltage Vg to be applied to the gate electrode 707 is set to 10 V. Channel hot electron injection occurs near the boundary between the channel region 703 and drain region 702 so that electrons are trapped in the silicon nitride film 706B.
By reversing the voltages applied to the source region 701 and drain region 702, electrons can be trapped in the silicon nitride film 706B near the boundary between the channel region 703 and source region 701. It is therefore possible to store data of two bits in one memory cell.
In reading data, the drain voltage Vd and substrate voltage Vsub are set to 0 V, the source voltage Vs is set to 1V and the gate voltage Vg is set to 3.3 V. In the state that electrons are trapped in the silicon nitride film 706B, an inversion region of a carrier concentration distribution is not formed in the channel region 703 in its end area on the side of the drain region 702. Current does not flow through the source and drain. In the state that electrons are not trapped in the silicon nitride film 706B, drain current flows through the source and drain. Since a depletion region extends from the source region 701 to the channel region 703 near the source region 701, the drain current is hardly influenced by a presence/absence of trapped carriers on the source region 701 side.
By reversing the source voltage Vs and drain voltage Vd, it is possible to detect whether electrons are trapped in the silicon nitride film 706B near the boundary between the source region 701 and channel region 703.
In erasing data, the substrate voltage Vsub is set to 0 V, the source voltage Vs is set to 5 V or a floating state, the drain voltage Vd is set to 5 V, and the gate voltage Vg is set to xe2x88x925 V. Holes are injected into the silicon nitride film 706B near the boundary between the drain region 702 and channel region 703, because of inter-band tunneling. Charges of trapped electrons are therefore neutralized.
By reversing the source voltage Vs and drain voltage Vd, holes can be injected into the silicon nitride film 706B near the boundary between the source region 701 and channel region 703.
The density distribution of electrons trapped in the silicon nitride film 706B by CHE injection has a peak toward the center of the channel region 703 more than the density distribution of holes injected by inter-band tunneling. In order to neutralize charges of electrons distributed toward the center of the channel region 703, a fairly large number of holes are required to be injected.
As the read/erase operations of a flash memory are repeated, the density distribution of electrons trapped in the silicon nitride film 706B is considered to extend toward the center of the channel region 703. Therefore, as the write/erase operations are repeated, it takes a long time to erase data by injecting holes.
During data write, it can be considered that in addition to CHE injection, secondary collision ionized hot electron injection occurs. When secondary collision ionized hot electron injection occurs, electrons are trapped in the silicon nitride film 706B in an area above the center of the channel region 703. The electrons trapped in the silicon nitride film 706B in the area above the center of the channel region 703 cannot be removed by hole injection. Therefore, as the write/erase operations are repeated, the threshold value gradually rises. According to evaluation experiments by the present inventor, although the write threshold value and erase threshold value of a memory cell immediately after manufacture were about 3.8 V and 2.5 V, respectively, the threshold values rose to about 4.6 V and 3.25 V after ten thousands repetitions of the write/erase operations.
FIG. 11B is a cross sectional view showing a flash memory disclosed in JP-A-9-252059.
In a surface layer of a p-type silicon substrate 710, an n-type source region 711 and an n-type drain region 712 are formed. Between the source and drain regions, a channel region 714 is defined. At the interface between the drain region 712 and the silicon substrate 710, an n-type impurity doped region 713 of a low impurity concentration is formed.
A gate insulating film 715 is formed on the surface of the channel region 714, and on this gate insulating film, a gate electrode 716 is formed. The gate insulating film 715 and gate electrode 716 are disposed spaced apart by some distance from both the source region 711 and drain region 712. An end portion of the drain electrode 716 on the drain region 712 side overlaps a portion of the low impurity concentration region 713.
An ONO film 717 covers the side walls of the gate electrode 716, the substrate surface between the gate electrode 716 and source region 711, and the substrate surface between the gate electrode 716 and drain region 712. The ONO film 717 has a three-layer structure of a silicon oxide film 717A, a silicon nitride film 717B and a silicon oxide film 717C. Side wall spacers 718 made of silicon oxide are formed on the surface of the ONO film 717.
If the impurity doped region 713 of the low impurity concentration is not formed, even if a voltage equal to or greater than the threshold voltage is applied to the gate electrode 716, a channel is not formed in the substrate surface layer between the gate electrode 716 and drain region 712. Since the memory cell shown in FIG. 11B has the n-type low impurity concentration region 713, current flows between the source and drain. On the source region 711 side, a depletion layer extends from the source region 711 to the side of the gate electrode 716 so that it is not necessary to form such a low impurity concentration region on this side.
In writing data, a positive voltage is applied to the source region 711 and a higher positive voltage is applied to the gate electrode 716 to make the drain region 712 enter a floating state. Electrons are trapped in the silicon nitride film 717B on the source region 711 side by avalanche hot electron injection. A voltage of 0 V may be applied to the drain region 712 to utilize CHE injection.
In erasing data, a positive voltage is applied to the source region 711 and a negative voltage is applied to the gate electrode 716. Holes are trapped in the silicon nitride film 717B on the source region 711 side by avalanche hot hole injection. Charges of trapped electrons are therefore neutralized. A gate voltage having a larger absolute value may be applied to drain electrons trapped in the silicon nitride film 717B to the channel region 714 by Fowler-Nordheim tunneling (FN tunneling).
In the conventional memory cell shown in FIG. 11B, the silicon nitride film is not disposed over the center of the channel region 714. It is therefore possible to prevent the density distribution of electrons trapped in the silicon nitride film from extending to the area above the center of the channel region 714. However, since the low impurity concentration region 713 is disposed on the drain region 712 side, electrons cannot be injected into the silicon nitride film 717B on the drain region 712 side. From this reason, only one bit of data can be stored in one memory cell.
FIG. 11C is a cross sectional view of a memory cell which is an improved version of the memory cell shown in FIG. 11B. In the memory cell shown in FIG. 11B, the side wall spacer 718 is made of silicon oxide. In the memory cell shown in FIG. 11C, a side wall spacer 720 made of polysilicon is used. Therefore, the substrate surface layer between the gate electrode 716 and drain region 710 is capacitively coupled to the gate electrode via the side wall spacer 720. This capacitive coupling enables to form the channel between the gate electrode 716 and drain region 712 so that the low impurity concentration region 713 shown in FIG. 11B is not formed.
The principle of writing and erasing data for the memory cell shown in FIG. 11C is similar to the operation principle of the memory cell shown in FIG. 11B. Since a low impurity concentration region is not disposed between the drain region 712 and channel region 714, data of two bits can be stored in the memory cell similar to the memory cell shown in FIG. 11A.
In the memory cell shown in FIG. 11C, a voltage applied across the source region 711 and gate electrode 716 is divided by a capacitor between the gate electrode 716 and side wall spacer 720 and a capacitor between the side wall spacer 720 and channel region 714. It is therefore necessary to raise the gate voltage when data is written or erased. If the gate voltage is raised too high, the gate insulating film 715 may be dielectrically broken.
If an electrostatic capacitor between the gate electrode 716 and side wall spacer 720 and an electrostatic capacitor between the side wall spacer 720 and channel region 714 change their capacitance, an electric field generated between the side wall spacer 720 and channel region 714 fluctuates, which may result in write error or erase error.
It is an object of the present invention to provide a semiconductor device capable of storing data of two bits in one memory cell and being driven at a low voltage, and to its manufacture method.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on a partial area of a surface of said semiconductor substrate; a gate electrode formed on said gate insulating film; a lamination film formed on a side wall of said gate electrode and on the surface of said semiconductor substrate on both sides of said gate electrode, conformable to the side walls and the surface, said lamination film having a structure of at least three layers, each of the three layers being made of insulating material, and a middle layer being made of material easier to trap carriers than other two layers; a side wall spacer made of conductive material and facing the side wall of said gate electrode and the surface of said semiconductor substrate via said lamination film; a conductive connection member electrically connecting said side wall spacer and said gate electrode; and impurity doped regions formed in a surface layer of said semiconductor substrate in areas sandwiching said gate electrode along a first direction parallel to the surface of said semiconductor substrate, edges of said impurity doped regions being disposed under said lamination film and not reaching boundaries of said gate electrode.
An FET has the impurity doped regions as its source and drain regions. A gate voltage is directly applied to the side wall spacers to control the carrier density in the channel region under the side wall spacers. If carriers are rapped in the lamination film by CHE injection and the like, the threshold value changes. Presence/absence of trapping carriers correspond to data of 0 and 1. By detecting a change in the threshold value, data can be read. By injecting carriers having charges opposite to those of the trapped carriers into the lamination film, stored data can be erased.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a gate insulating film formed on a channel region defined in a surface layer of a semiconductor substrate; source and drain regions formed in the surface layer in both side areas of the channel region; carrier trap films covering first and second areas and made of material easier to trap carriers than the gate insulating film, an upper surface of the gate insulating film having the first area on the source region side, the second area on the drain region side and a third area between the first and second areas; a coating film made of insulating material and covering surfaces of the carrier trap films; and a gate electrode continuously covering at least a surface from a boundary between the source region and channel region to a boundary between the drain region and channel region among surfaces of the coating film and the gate insulating film on the third area.
When carriers are trapped in the carrier trap film, the threshold value changes. By detecting a change in the threshold value, presence/absence of trapped carriers can be judged. If carriers are once trapped in the region near the center of the channel region, it becomes difficult to remove the trapped carriers. Since the carrier trap film is not disposed in the third area, trapped carriers can be removed easily.
According to another aspect of the present invention, there is provided a semiconductor device comprising: source and drain regions formed in a surface layer of a semiconductor substrate and spaced apart by some distance; an intermediate region formed in the surface layer between said source and drain regions, spaced apart by some distance from both said source and drain regions, and doped with impurities of the same conductivity type as said source and drain regions; gate insulating films covering a channel region between said source and intermediate regions and a channel region between said drain and intermediate regions; a first film covering said source, drain and intermediate regions and made of insulating material, said first film being thicker than said gate insulating films; a carrier trap film formed on each of the gate insulating films and made of material easier to trap carriers than said gate insulating films; a coating film made of insulating material and covering a surface of each of said carrier trap films; and a gate electrode covering said coating film and first film disposed in an area from one of the channel regions to the other of the channel regions via the intermediate region.
Drain current flows via the intermediate region. Since the intermediate region has the conductivity type same as that of the source and drain regions, drain current is hardly influenced even if carriers are trapped in the region over the intermediate area. Accordingly, even if carriers are trapped in an insulating film near the central area between the source and drain regions, the threshold value hardly changes.
As above, a conductive member is disposed on the lamination film including a carrier trap film, and a gate voltage is directly applied to the conductive member. It is therefore possible to write and erase data at a relatively low voltage. The carrier trap layer is not disposed over the center of the channel region or the intermediate region doped with impurities is disposed in the central area of the channel region. A change in the threshold voltage is therefore small even if write/erase operations are repeated.